A Power Mapping and Modeling System for Integrated Circuits

Overview

One of the biggest challenges for computer chip architects is figuring out the power supply and power distribution, because this limits the performance and reliability of semiconductor-based chips. However, the complex nature of modern multi-core processors, in addition to the way that power usage varies dep-ending on workload, makes it exceedingly difficult to model and measure power within the system.

Sherief Reda’s invention offers a method for modeling the power inside an integrated circuit by using the effects that all that energy creates. Reda measures the thermal infrared emissions of the processor during operation and under realistic loading conditions. This heat is related to the amount of power that flowed through the system during operation, and it allows Reda to accurately reconstruct the system’s power profile.

 Market Opportunity

Any firm designing and building chip must be able to accurately model power usage and management within the system, but modern multi-core processors use billions of transistors in an increasingly complex arrangement. The intricate nature of these processors, along with the varying workloads they take on, make it an arduous and challenging task to simulate the power usage in a “pre-silicon” manner—that is, simulating the system’s power usage before a task is undertaken.

Because of these difficulties, the industry, and researchers alike in recent years have begun to pursue the possibility of “post-silicon” power mapping, which reconstructs the processor’s power usage based on physical signals such as how much heat is created during use, which is directly related to how much power the system has used. A post-silicon approach that could overcome some of the inherent challenges of the approach, such as accurately translating heat signals into a power usage model, would be invaluable for chip architects.

Innovation and Meaningful Advantages

Post-silicon techniques that invert the thermal emissions captured from a chip and turn them into a power profile have greater promise than pre-silicon approaches, but they still face numerous challenges: the need for accurate thermal-to-power conversion, the need to remove data artifacts that can throw off the accuracy of the model, and leakage issues.

Reda and colleagues have created a novel and accurate framework to capture the relationship between temperature and power, while compensating for artifacts introduced by substituting traditional heat removal mechanisms with oil-based cooling mechanisms. Using leakage power models, they developed a method to analyze leakage variations, and they also devised a method to relate the actual power consumption of different blocks of the integrated circuit to the performance monitoring counter (PMC) measurements using empirical models. They have validated their system using a quad-core processor integrated circuit under different workload conditions, by reconstructing the dynamic and leakage power maps for different blocks within the processor.

Collaboration Opportunity

We are seeking an investment opportunity to further develop this innovative technology.

Principal Investigator

Sherief Reda, PhD
Professor of Engineering, Professor of Computer Science

IP Information

US Patent 10,175,705, Issued January 8, 2019

 

Contact

Brian Demers
Director of Business Development, School of Engineering and Physics
Brian_Demers@brown.edu 
Brown Tech ID: 2213
Patent Information:
For Information, Contact:
Brown Technology Innovations
350 Eddy Street - Box 1949
Providence, RI 02903
tech-innovations@brown.edu
401-863-7499
Inventors:
Sherief Reda
Abdullah Nowroz
Kapil Dev
Keywords:
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