Innovative Sublithographic Nanoscale Interfaces and Memory Architecture (Case 1545)

Principal Investigators:


John Savage, PhD, Professor

Department of Computer Science

Brown University

Providence, RI


Brief Description:


As computing devices become ever smaller, so do the accompanying microelectronic circuit boards and components.  New advanced techniques beyond the conventional lithography of silicon for etching patterns and circuits in semiconductor processing have been explored and developed.  As such, miniaturization of devices has significantly advanced not only personal consumer electronics, e.g., smart phones, for increasing power, functionality and portability, but has also greatly improved the patient care through implantable drug delivery and/or neuroprosthetic devices, among a plethora of other beneficial micro- / nano- scale devices.  To achieve fully-nanoscale systems, the newer technique of sublithography has been developed to address the size limitations and cost of lithography by the exploitation of seeding, molecular self-organization, and time-controlled growth and etch to define basic sizes of features.  In this way, semiconducting nanowires, of different materials or selective doping, can be grown via a catalyst/seed. 


Technologies to build nanoscale crosspoints and for storing non-volatile memory bits at the crosspoints of a nanoscale wire array are known, as is how doped silicon nanoscale wires can exhibit Field-Effect Transistor (FET) behavior.  It has also been shown that the doping profile or material composition along the axial dimension of a nanoscale wire can be controlled, and regular arrangements of nanoscale wires (parallel arrays of wires, crossed, orthogonal structures) have been established.  Further, non-volatile memories can be built, which are as tight as the nanoscale (sublithographic) wire pitch. 


Currently, however, manufacturing issues remain that involve the ability to program or read crosspoints, to apply a control voltage to an individual nanoscale wire, and to selectively read from a single nanoscale wire.  Hence, a critical weakness in the construction of fully nanoscale memory and logic arrays is the need for the construction of an interface that allows one to individually address the nanoscale from the microscale wires.  An approach using a decoder based on gold nanoparticle deposition has been employed, but not without manufacturing challenges associated with achieving uniform deposition and localization that can adversely affect function.  Therefore, a better way to individually address the nanoscale wires is needed. The invention offered below achieves this goal and provides further advantages.


The invention consists of methods and devices to control electric conduction on single nanoscale wires individually, from both lithographic/microscale and nanoscale control wires, so that individual crosspoints can be programmed and addressed.  Differently coded nanoscale wires provide independent nanoscale wire addressability.  As such, this novel technique bridges lithographic and sublithographic scales, whereby a collection of lithographic scale wires is able to uniquely select a single sublithographic scale wire from a collection of such sublithographic scale wires tightly packed at sublithographic pitches.  Furthermore, the innovation provides a fabrication process for building and integrating sublithographic scale logic based on decorated (modulation-doped or superlattice heterostructure) nanoscale wires, as well as for building sublithographic scale address decoders and sublithographic scale memories that can be addressed, read, and written from lithographic scale wires.  A stochastic assembly of sublithographic nanoscale interfaces and sublithographic nanoscale memory architecture is achieved. 


The unique address decoder in this invention is created by the self-assembly of randomly mixed differentially coded nanoscale wires into a parallel array, thereby realizing a microscale-to-nanoscale interface and bridging the gap from top-down lithographic processing to bottom-up self-assembly.  This differently coded nanoscale wire-based address decoder overcomes misalignment of nanoscale wires, allows the customization of nanoscale programmable computing arrays to personalize behavior and tolerate faults, and directly enables reliable nanoscale memory devices.  Moreover, the codes can be discovered with reasonable efficiency, and the addressing scheme offers tighter address coding, requires fewer novel processes, and uses standard semiconductor industry materials and dopants.


Schematically, the invention is a memory array comprised of nanoscale wires with controllable regions – axially and/or radially – distributed along the wires, for conduction.  In 1-, 2-, and 3- dimensional versions, memory locations are defined by crossing points between nanoscale and microscale wires, between perpendicular nanoscale wires, and between nanoscale wires located in different vertical layers, respectively. 


Applications include for use in fabricating advanced nanoscale semiconductor circuits for any number of microelectronic devices such as those used in/for telecommunications, miniaturized implantable biomedical device for drug or other therapeutic delivery, or in computing devices/memory, etc.  Further applications are as a basic research tool in the fields of microelectronics, computer science, biomedical engineering, among others.  Markets indicated are pharmaceutical – implantable medical devices; microelectronics; semiconductors; telecommunications; computer components – memory/circuit boards; scientific R&D tools; among others.




US patent 6,963,077 is issued (11/08/2005) 

Patent Information:
For Information, Contact:
Margaret Shabashevich,
Manager of Operations
Technology Ventures Office
Brown University
John Savage
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